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FPGAs Can Help Latency Sensitive Traders Achieve Better Executions
Traders Magazine Online News, April 24, 2017
In this Q&A with Traders Magazine, Louie De Luna, Director of Marketing at ALDEC, talks about trading technologies such as Field Programmable Gate Arrays, software and latency issues and how his firm looks to help high-frequency and other speed-dependent traders in their quest to achieve best execution.
Traders Magazine: Tell us little about ALDEC. What is the primary function/product output and what is the target demographic in the financial vertical?
De Luna: ALDEC was established in 1984. We are a verification technology and tool provider for FPGAs and ASICs. We are one of the pioneers in mixed-language RTL simulation and hardware-assisted verification, and we continue to support our customers in the areas of telecommunication, high performance computing and embedded systems. Using our FPGA verification tools, methodologies and expertise we would like to help the HFT industry to accelerate algorithms and data processing using FPGAs.
Louie DeLuna
TM: Measuring the value of FPGA enhanced functionality is a big focus for determining if, when and how a firm should be using FPGA and acceleration technologies. What is ALDEC’s role in this?
De Luna: The inherent re-programmability of FPGAs, deep pipelining structures and massive parallel compute resources have made FPGAs popular in HFT. The re-programmability aspect allows for new protocols to be supported using the same FPGA hardware. The deep pipelining and parallelism aspects allow for a predictable and ultra-low latency.
It is important to say FPGA is not an acceleration cure for every algorithm and data processing. FPGA are best to use for acceleration of algorithms where huge number of operations is performed on relatively small data. Expertise in FPGA definitely helps to achieve the best possible results considering the architecture and features. As a company, we have huge expertise in RTL porting and optimizations which can help CTO’s and Engineers in the financial vertical.
TM: Talk to us a little about the RTL Simulator for support. Can this system help firms better utilize FPGA.
De Luna: We’ve had our mixed-language RTL simulation technology for around 30 years now and we continue to enhance it. Our tool supports various language standards such as Verilog, VHDL, SystemVerilog(UVM) and SystemC for both Windows and Linux OS. Simulation is a standard part of the FPGA development flow employed prior to running the design in the FPGA board. Simulation enables engineers to check and debug the design for various test scenarios and strategies, where they have full visibility into the FPGA pin I/Os, internal registers and signals. Engineers can debug the design without having to recompile the FPGA binaries, and optimize the design for performance before running it in the FPGA board.
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